Method of fabricating semiconductor device
US6475865B1 · kind B1 · utility
25Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 26, 2000 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Jan 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02153
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device. A shallow trench isolation is formed by forming a well region, a gate oxide layer and a wiring layer prior to forming a trench in the substrate. The trench is then filled with silicon oxide layer doped with germanium, nitrogen, titanium or other refractory metal. In addition, a MOS device is also fabricated with a gate buried in the substrate with a shallow trench isolation filled with the doped silicon oxide layer formed therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.