Oxygen implantation for reduction of junction capacitance in MOS transistors
US6475868B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2000 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Aug 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Silicon-based, submicron-dimensioned MOS and/or CMOS transistor devices having substantially reduced source/drain junction-to-semiconductor substrate capacitance are formed by implanting oxygen atoms and/or molecules just below source/drain implant regions. Implantation conditions are selected to provide a peak oxygen implant concentration at a depth just below the ultimate source/drain junction depth. Subsequent thermal processing at elevated temperature results in source/drain dopant diffusion/activation and formation of a silicon oxide barrier layer or stratum just below the ultimate source/drain junction depth, thereby substantially reducing junction-to-substrate capacitance of refractory metal silicide-contact devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.