Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6475869B1 · kind B1 · utility
577Cited by
18References
20Claims
0Family size
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Key dates
| Filing date | Feb 26, 2001 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Feb 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
Abstract
A method of manufacturing an integrated circuit with a channel region containing germanium. The method can provide a double planar gate structure. The gate structure can be provided over lateral sidewalls of channel region. The semiconductor material containing germanium can increase the charge mobility associated with the transistor. An epitaxy process can form the channel region. A silicon-on-insulator can be used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.