Shallow trench isolation elevation uniformity via insertion of a polysilicon etch layer
US6475875B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2001 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Jul 9, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming insulator filled, shallow trench isolation (STI), regions in a semiconductor substrate, featuring a disposable polysilicon stop layer used to allow uniform insulator fill to be obtained, independent of shallow trench width, has been developed. The process features filling shallow trench shapes with a first high density plasma (HDP), deposited silicon oxide layer, followed by the deposition of the thin polysilicon stop layer, and a second HDP silicon oxide layer. After a planarizing chemical mechanical polishing procedure residual regions of the second HDP silicon oxide, still remaining in regions overlying the insulator filled shallow trench shapes, are selectively removed using the thin polysilicon layer as a stop layer. The polysilicon layer is then thermally oxidized. The thickness of the polysilicon layer can be varied such that the resultant polysilicon oxide layer serves to alleviate the possible oxide loss in the STI regions during subsequent clean processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.