Devices and methods for addressing optical edge effects in connection with etched trenches
US6475884B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2001 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Aug 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/665
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a first aspect of the invention, a modified semiconductor substrate is provided. The modified substrate comprises: (1) a semiconductor substrate; (2) at least one buffer layer provided over at least a portion of the substrate; and (3) a plurality of trenches comprising (a) a plurality of internal trenches that extend into the semiconductor substrate and (b) at least one shallow peripheral trench that extends into the at least one buffer layer but does not extend into the semiconductor substrate. In another aspect, a method of selectively providing trenches in a semiconductor substrate is provided. According to a further aspect of the invention, a trench DMOS transistor structure that includes at least one peripheral trench and a plurality of internal trenches is provided. The structure comprises: (1) a substrate of a first conductivity type; (2) a body region on the substrate having a second conductivity type, wherein the peripheral and internal trenches extend through the body region; (3) an insulating layer that lines each of the peripheral and internal trenches; (4) a first conductive electrode overlying each insulating layer; and (5) source regions of the first conductivity …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.