Method of forming vias in silicon carbide and resulting devices and circuits
US6475889B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 11, 2000 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Apr 11, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device on a first surface of a silicon carbide substrate and with at least one metal contact for the device on the first surface of the substrate. The opposite, second surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished second surface of the silicon carbide substrate to define a predetermined location for a via that is opposite the device metal contact on the first surface; etching the desired via through the desired masked location until the etch reaches the metal contact on the first surface; and metallizing the via to provide an electrical contact from the second surface of the substrate to the metal contact and to the device on the first surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.