Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology

US6475890B1 · kind B1 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventor

• Bin Yu · Cupertino, US

Key dates

• Filing date: Feb 12, 2001
• Grant date: Nov 5, 2002
• Expiry date: Feb 12, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/673

Abstract

For fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, a pillar of semiconductor material is formed on a layer of buried insulating material. The pillar has a top surface and first and second side surfaces, and the pillar has a width, a length, and a height. A masking structure is formed on a center portion of the top surface of the pillar along the length of the pillar. A top portion of the height of the pillar is etched from exposed surfaces of the top surface of the pillar down to a bottom portion of the height of the pillar to form an upside down T-shape for the pillar. A gate dielectric material is deposited on any exposed surface of the semiconductor material of the pillar for a gate length along the length of the pillar. A gate electrode material is deposited on the gate dielectric material to surround the pillar for the gate length of the pillar. A drain and source dopant is implanted into exposed regions of the pillar to form a drain of the field effect transistor on a first side of the gate electrode material along the length of the pillar and to form a source of the field effect transistor on a second side o…