Process for fabricating a floating gate of a flash memory in a self-aligned manner

US6475894B1 · kind B1 · utility

Assignee

• NANYA TECHNOLOGY CORPORATION · TW

Inventors

• Chung-Lin Huang · Taichung, TW
• Sheng-Tsung Chen · Tainan, TW
• Chi-Hui Lin · Taipei, TW

Key dates

• Filing date: Jan 18, 2002
• Grant date: Nov 5, 2002
• Expiry date: Jan 18, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

The present invention provides a process for fabricating a floating gate of a flash memory. First, an isolation region is formed in a semiconductor substrate and the isolation region has a height higher than the substrate. A gate oxide layer and a first polysilicon layer are then formed. The first polysilicon layer is formed according to the contour of the isolation region to form a recess in the first polysilicon layer. A sacrificial insulator is filled into the recess. The first polysilicon layer is then selectively removed in a self-aligned manner using the sacrificial insulator as a hard mask to expose the isolation region. A polysilicon spacer is formed on the sidewalls of the first polysilicon layer. A first mask layer is formed on the isolation region, the sacrificial insulator in the recess is removed, and a floating gate region is defined. Then, the surfaces of the first polysilicon layer and polysilicon spacer in the floating gate region are oxidized to form a polysilicon oxide layer. Finally, the polysilicon oxide layer is used as a mask to pattern the underlying first polysilicon layer and polysilicon spacer in a self-aligned manner to form a floating gate. During the o…