Method for producing trenches for DRAM cell configurations

US6475919B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Lothar Brencher · Radeberg, DE
• Maik Stegememann · Dresden, DE
• Uwe Rudolph · Dresden, DE

Key dates

• Filing date: Jan 3, 2001
• Grant date: Nov 5, 2002
• Expiry date: Jan 3, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/3083
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The invention relates to a method for producing trenches for manufacturing storage capacitors in DRAM cell configurations. In the method, a two-stage hard mask having a first mask layer (1) and an underlying second mask layer (2) is used. A resist mask is applied to the mask layers (1, 2). The trenches are structured by etching processes, in which, in a first etching process, the first mask layer (1) is etched selectively with respect to the resist mask, and in a second etching process, the second mask layer (2) is etched selectively with respect to the first mask layer (1).