Integrated memory having memory cells that each include a ferroelectric memory transistor

US6477078B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Heinz Honigschmid · Starnberg, DE
• Marc Ullmann · Hamburg, DE

Key dates

• Filing date: Sep 25, 2001
• Grant date: Nov 5, 2002
• Expiry date: Sep 25, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/22
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An integrated memory has word lines that run in a first direction, and bit lines and control lines that run in a second direction, which is perpendicular to the first direction. A controllable path of each memory transistor connects one of the bit lines to one of the control lines. The control electrode of each memory transistor is connected to one of the word lines. Since the bit lines and control lines run in the same direction and are thus arranged parallel to one another, they can be arranged within a common wiring plane of the integrated memory. Since the terminals of the controllable path are usually likewise arranged in a common wiring plane, for example in a substrate of the integrated memory, it is possible, to arrange the bit lines and control lines in the same wiring plane as the controllable path of the transistors.