SOI device with self-aligned selective damage implant, and method
US6479866B1 · kind B1 · utility
88Cited by
7References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 14, 2000 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Nov 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A transistor on an SOI wafer has a subsurface recombination area at least partially within its body. The recombination area includes one or more damaged recombination regions. The damaged recombination region(s) may be formed by a damaging implant into a surface semiconductor layer, for example through an open portion of a doping mask, the opening portion created for example by removal of a dummy gate. Alignment of the damaged recombination region(s) is improved by forming the source and drain of the transistor prior to removal of the dummy gate, using the dummy gate as a doping mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.