Retrograde well structure for a CMOS imager

US6483129B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Howard E. Rhodes · Boise, US
• Mark Durcan · Boise, US

Key dates

• Filing date: Aug 1, 2001
• Grant date: Nov 19, 2002
• Expiry date: Aug 1, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10F39/803

Abstract

A retrograde well structure for a CMOS imager that improves the quantum efficiency and signal-to-noise ratio of the imager. The retrograde well comprises a doped region with a vertically graded dopant concentration that is lowest at the substrate surface, and highest at the bottom of the well. A single retrograde well may have a single pixel sensor cell, multiple pixel sensor cells, or even an entire array of pixel sensor cells formed therein. The highly concentrated region at the bottom of the retrograde well repels signal carriers from the photosensor so that they are not lost to the substrate, and prevents noise carriers from the substrate from diffusing up into the photosensor. Also disclosed are methods for forming the retrograde well.