Capacitor with extended surface lands and method of fabrication therefor
US6483692B2 · kind B2 · utility
18Cited by
6References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2000 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Dec 19, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A capacitor (FIGS. 6-9) includes one or more extended surface lands (604, 704, 804, 904, FIGS. 6-9). In one embodiment, each extended surface land is a land on a top or bottom surface of the capacitor, having a land length that is equal to at least 30% of the width (614, FIG. 6) of the capacitor or 20% of the length (914, FIG. 9) of the capacitor. When embedded within an integrated circuit package (1102, FIG. 11), two or more vias (1112) can be electrically connected to the extended surface lands (1108).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.