Method for generating memory addresses for testing memory devices
US6483773B1 · kind B1 · utility
2Cited by
29References
33Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 3, 2000 |
| Grant date | Nov 19, 2002 |
| Priority date | — |
| Expiry date | Aug 3, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A counter internal to a memory device for generating memory addresses in physical or logical sequence in non-redundant or redundant memory space, counting up or down in increments of the user's choice. The counter may be advantageously used to generate memory addresses for functional testing of the memory cells within the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.