Flash memory with less susceptibility to charge gain and charge loss
US6486506B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2000 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | Mar 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit is designed to reduce charge gain and charge loss in a flash memory or flash programmable read-only memory. Charge gain and loss caused by moisture or hydrogen diffusion or alternately small contact-to-floating gate distance is reduced by a capping layer disposed over a gate stack and a base layer of the flash memory. The capping layer includes a buffer layer, a first insulative layer, and a second insulative layer. The etch characteristics of at least the first and second insulative layer differs from an interlevel dielectric to control the dimensions of a contact extending through the interlevel dielectric and the capping layer to the base layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.