Semiconductor package with warpage resistant substrate
US6486537B1 · kind B1 · utility
16Cited by
26References
23Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 19, 2001 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | Mar 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package and a method for fabricating a semiconductor package are disclosed. The semiconductor package includes semiconductor chip attached to a circuit board that includes at least one lateral slot formed through the circuit board. Provision of the slot reduces stresses in the circuit board that are manifested by warpage. The semiconductor chip may be positioned in a central aperture of the circuit board and held therein by hardened encapsulant material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.