Hybrid dielectric structure for improving the stiffness of back end of the line structures
US6486557B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 29, 2000 |
| Grant date | Nov 26, 2002 |
| Priority date | — |
| Expiry date | Feb 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-level, coplanar copper damascene interconnect structure on an integrated circuit chip includes a first planar interconnect layer on an integrated circuit substrate and having plural line conductors separated by a dielectric material having a relatively low dielectric constant and a relatively low elastic modulus. A second planar interconnect layer on the first planar interconnect layer comprises a dielectric film having an elastic modulus higher than in the first planar interconnect layer and conductive vias therethrough. The vias are selectively in contact with the line conductors. A third planar interconnect layer on the second planar interconnect layer has plural line conductors separated by the dielectric material and selectively in contact with the vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.