High surface quality GaN wafer and method of fabricating same
US6488767B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2001 |
| Grant date | Dec 3, 2002 |
| Priority date | — |
| Expiry date | Jun 8, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/21
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A high quality wafer comprising AlxGayInzN, wherein 0<y≦1 and x+y+z=1, characterized by a root mean square surface roughness of less than 1 nm in a 10×10 &mgr;m2 area at its Ga-side. Such wafer is chemically mechanically polished (CMP) at its Ga-side, using a CMP slurry comprising abrasive particles, such as silica or alumina, and an acid or a base. The process of fabricating such high quality AlxGayInzN wafer may include steps of lapping, mechanical polishing, and reducing internal stress of said wafer by thermal annealing or chemical etching for further enhancement of its surface quality. The CMP process is usefully employed to highlight crystal defects on the Ga-side of the AlxGayInzN wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.