Process for fabricating integrated multi-crystal silicon resistors in MOS technology, and integrated MOS device comprising multi-crystal silicon resistors

US6489664B2 · kind B2 · utility

Assignee

• STMicroelectronics SA

Inventors

• Danilo Re · Bernareggio, IT
• Massimo Monselice · Offanengo, IT
• Paola Maria Granatieri · Milano, IT

Key dates

• Filing date: May 24, 2001
• Grant date: Dec 3, 2002
• Expiry date: May 24, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/811

Abstract

A fabrication process and an integrated MOS device having multi-crystal silicon resisters are described. The process includes depositing a multi-crystal silicon layer on top of a single-crystal silicon body; forming silicon oxide regions on top of the multi-crystal silicon layer in zones where resistors are to be produced; depositing a metal silicide layer on top of and in contact with the multi-crystal silicon layer so as to form a double conductive layer; and shaping the conductive layer to form gate regions, of MOS transistors. During etching of the double conductive layer, the metal silicide layer on top of the silicon oxide regions is removed and the silicon oxide regions form masking regions for the multi-crystal silicon underneath, so as to form resistive regions having a greater resistivity than the gate regions.