Method of erasing a non-volatile memory cell using a substrate bias
US6490205B1 · kind B1 · utility
32Cited by
10References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 26, 2000 |
| Grant date | Dec 3, 2002 |
| Priority date | — |
| Expiry date | Dec 15, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0475
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of erasing a memory cell with a substrate that has a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains an initial amount of charge. The method includes applying a constant first voltage across the gate and applying a second constant voltage across said the region. A third constant voltage is applied in a region of the substrate outside of the first and second regions so that a first portion of the first amount of charge is removed from the charge trapping region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.