Wafer scale encapsulation for integrated flip chip and surface mount technology assembly
US6492071B1 · kind B1 · utility
2Cited by
8References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2000 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Sep 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device and process for applying mixtures of adhesive formulations combined with solder flux such that flip chips may be rapidly encapsulated with such combinations without interfering with subsequent wafer processing steps are provided. Also provided is a wafer stencil designed in such a manner that the saw kerf lines separating individual chip dies are protected from coming into contact with the formulation. Extrusion screening using such wafer stencil is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.