Trilayer/bilayer solder bumps and fabrication methods therefor
US6492197B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 23, 2000 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | May 23, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10992
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Solder bumps are fabricated by plating a first solder layer on an underbump metallurgy, plating a second solder layer having higher melting point than the first solder layer on the first solder layer and plating a third solder layer having lower melting point than the second solder layer on the second solder layer. The structure then is heated to below the melting point of the second solder layer but above the melting point of the first solder layer and the third solder layer, to alloy at least some of the first solder layer with at least some of the underbump metallurgy and to round the third solder layer. Accordingly, a trilayer solder bump may be fabricated wherein the first and third layers melt at lower temperatures than the second solder layer, to thereby round the outer surface of the solder bump and alloy the base of the solder bump to the underbump metallurgy, while allowing the structure of the intermediate layer to be preserved. Solder bump fabrication as described above may be particularly useful with lead-tin solder wherein the first solder layer is eutectic lead-tin solder, the second solder layer is lead-tin solder having higher lead content than eutectic lead-tin so…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.