Method for eliminating crack damage induced by delaminating gate conductor interfaces in integrated circuits

US6492247B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• William H. Guthrie · South Burlington, US
• Andreas Kluwe · South Burlington, US
• Michael Ruprecht · Landsberg am Lech, DE

Key dates

• Filing date: Nov 21, 2000
• Grant date: Dec 10, 2002
• Expiry date: Nov 29, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for manufacturing integrated circuits (“IC”) on wafers to manage crack damage in the ICs such that crack propagation into the IC active array is reduced or eliminated. The method provides for a defined separation or divide of the IC gate conductor from the IC crack stop or IC edge. The method is especially useful in managing crack damage induced through the delamination of one or more of the gate conductor surface interfaces as a result of the IC wafer dicing process. Circuits or chips manufactured according to the methods disclosed are also taught.