Process for making a planar integrated circuit interconnect
US6492259B2 · kind B2 · utility
8Cited by
10References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2001 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Jul 19, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/926
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a planar integrated circuit interconnect and process of fabrication. The planar integrated circuit comprises a substrate having a first line wire formed in the substrate, a dielectric layer formed on the substrate, a second line wire formed in the dielectric layer, a contact via formed within the dielectric layer extending through the dielectric layer from the second line wire to the first line wire, and a dummy via which extends into the dielectric layer and is filled with a low dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.