Control of transistor performance through adjustment of spacer oxide profile with a wet etch
US6492275B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2000 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Jan 21, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of patterning sidewall spacers are provided. In one aspect, a method of fabricating a circuit device includes forming a gate on a substrate and forming a first oxide spacer and a second oxide spacer adjacent to the gate. The width of the gate and the first and second oxide spacers is measured. The widths of the first and second oxide spacers are trimmed if the width of the gate and the first and second oxide spacers exceeds a preselected maximum value by exposing the first and second oxide spacers to a solution of ammonium hydroxide, hydrogen peroxide and water for a preselected like and rinsing with deionized water. Spacer width may be finely tuned to reduce the risk of weak overlap and to improve device characteristics through shorter channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.