Method for manufacturing a high voltage MOSFET device with reduced on-resistance
US6492679B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2001 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Aug 3, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A high voltage MOSFET device (100) has a well region (113) with two areas. The first area (110) has a high dopant concentration and the second area (112) has a low dopant concentration. Inside the well region a region of a secondary conductivity type (108) is formed. The second area (110) is typically underlying a gate region (105). The lower doping concentration in that area helps to increase the breakdown voltage when the semiconductor device is blocking voltage and helps to decrease the on-resistance when the semiconductor device is in the “on” state. The MOSFET device further has a p-top layer (108) which is disposed on the top surface of the well region and then driven into the well region by annealing the MOSFET device at a high temperature in an inert atmosphere.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.