Method for detecting and classifying scratches occurring during wafer semiconductor processing
US6493645B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 11, 2000 |
| Grant date | Dec 10, 2002 |
| Priority date | — |
| Expiry date | Jan 11, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This method for detecting and classifying a scratch on a semiconductor wafer, in accordance with the invention, first defines a coordinate system on the wafer. The method creates a list of failed cells according to coordinates corresponding to the cell failures on the wafer. The number of failed cells, in total, is determined. Through calculating the standard deviation of the failed cells at a plurality of different angles, based on the list of failed cells and the total number of failed cells, a determination is made as to whether the wafer has a potential scratch. Plotting the standard deviations versus the number of failed cells and comparing that point to other known points determines the presence of a scratch. The steps of detecting and classifying scratches occurring on wafers may be performed by a computer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.