Technique to improve deep trench capacitance by increasing surface thereof
US6495411B1 · kind B1 · utility
Assignees
Inventor
Key dates
| Filing date | Oct 10, 2000 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Oct 10, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/964
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating deep-submicron DRAMs containing a deep trench capacitor with enlarged sidewall surface for improved storage capacitance. It includes the main steps of: (a) forming a silicon substrate having a (110) crystalline plane and a (111) crystalline plane; (b) forming a vertically extending deep trench into a crystalline silicon substrate; (c) filling the deep trench with a first dielectric material to form a first dielectric filler layer; (d) etching back the first dielectric filler layer to a first depth; (e) forming a dielectric collar from a second dielectric material which hangs on the sidewall of the deep trench extending from the opening of the trench to the first depth; (f) removing the first dielectric filler layer with a selective etching process; and (g) under a carefully timed exposure, using an isotropic etching solution which has high etching rate in the (110) plane and low etching rate in the (111) plane to form a roughened surface on the bottom surface of the deep trench. A roughened surface has a root-mean-square (RMS) surface roughness of at least 100 å can be obtained. Since this method does not require enlargement in either the vertical dir…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.