Structure for masking integrated capacitors of particular utility for ferroelectric memory integrated circuits

US6495413B2 · kind B2 · utility

Assignees

• RAMTRON INTERNATIONAL CORPORATION · US
• Ulvac Japan, Ltd. · JP

Inventors

• Shan Sun · Wingdale, US
• George Hickert · Colorado Springs, US
• Diana Johnson · Wrenshall, US
• John Ortega · Spring Hill, US
• Eric Dale · Colorado Springs, US
• Masahisa Ueda · Susono, JP

Key dates

• Filing date: Feb 28, 2001
• Grant date: Dec 17, 2002
• Expiry date: Feb 28, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/32139
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for fabricating integrated capacitors, of particular utility in forming a ferroelectric capacitor array for a ferroelectric memory integrated circuits, begins with provision of a substrate. The substrate is typically a partially-processed CMOS integrated circuit wafer coated with an adhesion layer. Upon the substrate is deposited a bottom electrode layer, typically of noble metal, a dielectric layer, typically doped PZT, and a top electrode layer, typically a noble metal oxide. Next is deposited a hardmask layer of strontium ruthenium oxide, followed by a photoresist layer. The photoresist layer is aligned, exposed, developed, and cured as known in the art of integrated circuit photolithography. The resulting stack is then dry etched to remove undesired portions of the hardmask layer, the top electrode layer, and the dielectric layer. A principle advantage of the process is that a single photomasking operation is sufficient to define the top electrode and dielectric layers.