Method of fabricating a dielectric layer
US6495474B1 · kind B1 · utility
49Cited by
14References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 11, 2000 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Sep 11, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device having a gate dielectric layer. The method includes the step of ion implanting at least one of Zr, Hf, La, Y, Al, Ti and Ta into the gate dielectric layer at low implant energy level to increase the dielectric constant of the dielectric layer. Subsequently, the implanted gate dielectric layer is annealed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.