Memory cell configuration

US6496401B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventor

• Rolf Weis · Dresden, DE

Key dates

• Filing date: May 31, 2001
• Grant date: Dec 17, 2002
• Expiry date: May 31, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10

Abstract

A memory cell configuration has memory cells, each with a trench capacitor in a trench and a vertical transistor, which is used as a selection transistor. The trench capacitors in adjacent memory cells are arranged next to a bit line and are connected to the bit line via their selection transistor. Adjacent trench capacitors connected to a bit line are arranged alternately on the two sides of the bit line.