Chip ID register configuration
US6496423B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2001 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Jul 3, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/5444
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A chip ID register configuration includes a shift register having individual stages. A fuse device connected to the shift register has fuses each substantially assigned to a respective one of the individual stages of the shift register, for identifying a chip having various required and non-required categories. The fuse device stores information from the categories to be read out serially through the shift register to identify the chip. A memory unit stores items of defined information. A logic circuit reads the fuse device for the required category and reads one of the items of defined information stored in the memory unit for the non-required category, on the basis of the categories of the chip to be identified. Standard testing of different chips is made possible while taking up little chip area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.