Multiple bit line column redundancy
US6496425B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2000 |
| Grant date | Dec 17, 2002 |
| Priority date | — |
| Expiry date | Aug 21, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices having multiple bit line column redundancy are suited for high-performance memory devices, with particular reference synchronous non-volatile memory devices. Such memory devices include bloc of memory cells arranged in columns with each column of memory cells coupled to a local line. Such memory devices further include global bit lines having multiple local bit lines selectively coupled to each global bit line, with each global bit line extending to local bit lines in each memory block of a memory sector. Global bit lines are coupled to sensing devices generally in pairs. Repair of one or more defective columns of memory cells within a sector is effected by providing a redundant grouping of memory cells having a redundant sense amplifier, global bit lines and local bit lines. Each grouping of memory cells contains four or more columns of memory cells. Access requests directed to memory cells within a grouping of memory cells containing a defective column are redirected to a redundant grouping of memory cells. Thus, a defect in one column of memory cells results in replacement of four or more columns of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.