Body-tied-to-body SOI CMOS inverter circuit
US6498371B1 · kind B1 · utility
14Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2001 |
| Grant date | Dec 24, 2002 |
| Priority date | — |
| Expiry date | Jul 31, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/967
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An SOI CMOS inverter circuit in which a silicide layer in combination with body tie regions tie a p-type body region and an n-type body region together. At the same time, however, the body regions remain floating electrically so that the benefits of SOI are maintained. The silicide layer permits excess carriers to be recombined via the respective body regions so that the body region potential does not get modulated by generation/recombination effects. Thus, a hysteresis effect in the inverter circuit will be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.