Structure and method of semiconductor via testing
US6498384B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 5, 2000 |
| Grant date | Dec 24, 2002 |
| Priority date | — |
| Expiry date | Dec 5, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/92
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer having a via test structure is provided which includes a semiconductor substrate having a plurality of semiconductor devices. A dielectric layer deposited over the semiconductor substrate has second and fourth channels unconnected to the plurality of semiconductor devices. A via dielectric layer deposited over the channel dielectric layer has first and second vias and third and fourth vias respectively open to opposite ends of the second channel and the fourth channel. A second dielectric layer over the via dielectric layer has first, third, and fifth channels respectively connected to the first via, the second and third vias, and the fourth via. The first channel, the first via, the second channel, the second via, the third channel, the third via, the fourth channel, the fourth via, and the fifth channel are connected in series and the first and fifth channel are probed to determine the presence or absence of voids in the vias.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.