Three step write process used for a nonvolatile NOR type EEPROM memory
US6498752B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2001 |
| Grant date | Dec 24, 2002 |
| Priority date | — |
| Expiry date | Aug 27, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3459
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a novel method for erasing an ETOX type and an AND type NOR flash memory arrays. The operations of the methods includes block erase which increases the Vt of the memory cell, block erase verify to check if the Vt of the erased cell is greater than a predetermined voltage Vtoff, page reverse program which reduces the Vt of the memory cell below a predetermine voltage Vtmax, reverse program verify which checks that the Vt of the memory cell is below Vtmax, page correction which corrects the Vt of cells on a page basis to be above a predetermined voltage Vtmin, and correction verify which checks that the Vt of the memory cells is above Vtmin. According to the present invention, the erase operation is performed to increase the Vt of erased cells by applying the positive high voltages to the selected word lines with bit lines and source lines grounded. The reverse program operation is performed to decrease the Vt of erased cells by applying the negative high voltage to the selected word lines with the source lines and bit lines grounded. For the ETOX cell an FN tunneling scheme is utilized for the Erase operation and CHE for the correction operation. The …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.