Apparatus for adjusting delay of a clock signal relative to a data signal
US6499111B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 16, 2001 |
| Grant date | Dec 24, 2002 |
| Priority date | — |
| Expiry date | Jul 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/104
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting circuit accepts a plurality of control signals each arranged to control passgates arranged in columns, with one column being controlled by a respective one of the control signals. A clock signal passes in parallel manner through a variety of delay gates, and each delay gate is coupled in series with one of the passgates. By selecting a path through desired passgates, one delay path is selected and the delay time added to the clock signal. This delayed clock signal is used to control the data passing circuit, which controls when data is output to the output terminals relative to the original clock signal. The control signals are created by selectively coupling or decoupling the control signals from a static voltage, and fuses or antifuses can be used to facilitate this coupling or decoupling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.