Method for fabricating a ferroelectric memory configuration

US6500677B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Renate Bergmann · Hersbruck, DE
• Christine Dehm · Koblenzer Straße, DE
• Thomas Roehr · Yokohama, JP
• Georg Braun · Hersbruck, DE
• Heinz Hoenigschmid · Starnberg, DE
• Gunther Schindler · Hersbruck, DE

Key dates

• Filing date: Dec 26, 2001
• Grant date: Dec 31, 2002
• Expiry date: Dec 26, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B53/30

Abstract

The invention provides a method. In a first step of a method for fabricating a ferroelectric memory configuration, there is provided a substrate having a multiplicity of memory cells. Each of the memory cells has at least one select transistor, at least one short-circuit transistor, and at least one ferroelectric capacitor. The transistors are connected in an electrically conductive manner to a first of the electrodes of the ferroelectric capacitor. In the next step, at least one electrically insulating layer is applied. In the next step, at least one contact hole for connecting a second electrode of the ferroelectric capacitors is produced. Next, contact holes for connecting the short-circuit transistors are produced. Next, the contact holes are filled with electrically conductive material. Next, an electrically conductive layer is applied and patterned, so that the second electrodes of the ferroelectric capacitors are each conductively connected to the short-circuit transistors.