Thomas Roehr
38Patents
10h-index
30Co-inventors
75Inventor score
Filing activity: Aug 9, 2001 → Mar 1, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7251152B2 | Memory circuit having memory cells which have a resistance memory element | Physics | 63 | Expired |
| US7215568B2 | Resistive memory arrangement | Physics | 60 | Expired |
| US6972427B2 | Switching device for reconfigurable interconnect and method for making the same | Electricity | 19 | Expired |
| US6577527B2 | Method for preventing unwanted programming in an MRAM configuration | Physics | 15 | Expired |
| US7499349B2 | Memory with resistance memory cell and evaluation circuit | Physics | 14 | Active |
| US7289350B2 | Electronic device with a memory cell | Physics | 11 | Expired |
| US7372716B2 | Memory having CBRAM memory cells and method | Physics | 11 | Expired |
| US7257013B2 | Method for writing data into a memory cell of a conductive bridging random access memory, memory circuit and CBRAM memory circuit | Physics | 11 | Expired |
| US7187602B2 | Reducing memory failures in integrated circuits | Physics | 10 | Expired |
| US7561460B2 | Resistive memory arrangement | Physics | 10 | Active |
| US6972983B2 | Increasing the read signal in ferroelectric memories | Physics | 9 | Expired |
| US7327603B2 | Memory device including electrical circuit configured to provide reversible bias across the PMC memory cell to perform erase and write functions | Physics | 9 | Expired |
| US7495945B2 | Non-volatile memory cell for storage of a data item in an integrated circuit | Physics | 9 | Active |
| US6639824B1 | Memory architecture | Physics | 7 | Expired |
| US6500677B2 | Method for fabricating a ferroelectric memory configuration | Electricity | 7 | Expired |
| US7092304B2 | Semiconductor memory | Physics | 7 | Expired |
| US6791871B2 | MRAM configuration | Physics | 6 | Expired |
| US7737428B2 | Memory component with memory cells having changeable resistance and fabrication method therefor | Emerging Cross-Sectional Technologies | 6 | Expired |
| US6826099B2 | 2T2C signal margin test mode using a defined charge and discharge of BL and /BL | Physics | 6 | Expired |
| US6724026B2 | Memory architecture with memory cell groups | Electricity | 6 | Expired |
| US6501686B2 | Electronic driver circuit for word lines in a memory matrix, and memory apparatus | Physics | 5 | Expired |
| US6707736B2 | Semiconductor memory device | Physics | 5 | Expired |
| US7184317B2 | Method for programming multi-bit charge-trapping memory cell arrays | Physics | 5 | Expired |
| US6584009B1 | Memory integrated circuit with improved reliability | Physics | 5 | Expired |
| US6920059B2 | Reducing effects of noise coupling in integrated circuits with memory arrays | Physics | 4 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.