Test fixture for future integration
US6500699B1 · kind B1 · utility
9Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2000 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Aug 3, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
According to one aspect of the disclosure, the present invention provides methods and arrangements for testing a flip chip SOI semiconductor device after the back side of the chip has been thinned to expose a selected region in the substrate. For some chips, thinning removes substrate material useful for drawing heat away from the internal circuitry when the circuitry is running at high speeds. To compensate for this material loss, a special test fixture having a passive, corrosion-resistant heat-dissipating device is arranged to draw heat from the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.