Method of forming sub-lithographic spaces between polysilicon lines
US6500756B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2002 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Jun 28, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming spaces between polysilicon lines can include patterning structures having top SiON layers and bottom amorphous carbon layers where the structures are located over a polysilicon layer and are separated by a first width, forming amorphous carbon spacers along lateral side walls of the patterned structures, etching apertures into the polysilicon layer not covered by the amorphous carbon spacers and the patterned structures where the apertures in the polysilicon layer between adjacent patterned structures have a second width, and ashing away the amorphous carbon spacers and the patterned structures. The second width is less than the first width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.