Logic/memory circuit having a plurality of operating modes
US6501296B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2001 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Jul 24, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17792
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory array having a read mode and a write mode is addressed using separate read and write decoders. The write decoder is used to write bit values to one column of the array. A hard-wired read decoder is utilized to further increase the operating speed during the memory read mode. In one embodiment, a separate read bit line is provided to facilitate faster read operations. In an exemplary embodiment, the write decoder receives two input signals and generates four write address signals on write word lines that are transmitted to the columns of programmable elements of a logic/memory array. The hard-wired read decoder also receives the same two input signals, and generates eight read address signals on two read word lines, two read address signals being transmitted to each column of the logic/memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.