Method for reducing peak to peak jitter in a dual-loop delay locked loop
US6501328B1 · kind B1 · utility
6Cited by
2References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2001 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Aug 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for reducing power supply noise in the power supply system of a delay locked loop has been developed. The method includes powering up a delay locked loop and inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the delay locked loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.