Dynamic random access memory (DRAM) capable of canceling out complementary noise developed in plate electrodes of memory cell capacitors
US6501672B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 2000 |
| Grant date | Dec 31, 2002 |
| Priority date | — |
| Expiry date | Sep 6, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/211
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic RAM comprising a plurality of word lines respectively connected to address select terminals of a plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to input/output terminals of the plurality of dynamic memory cells and placed in directions opposite to one another, and a sense amplifier array which is supplied with an operating voltage according to an operation timing signal and comprises a plurality of latch circuits for respectively amplifying the differences in voltage between the complementary bit line pairs. In the dynamic RAM, common electrodes provided, in opposing relationship to storage nodes corresponding to connecting points between address select MOSFETs and information storage capacitors of the plurality of dynamic memory cells, on both sides of the sense amplifier array are connected to one another by wiring using the common electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.