Method of forming a metal-insulator-metal capacitor for dual damascene interconnect processing and the device so formed
US6504203B2 · kind B2 · utility
5Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2001 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Feb 16, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/957
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method of forming a capacitor in a last metal wiring layer, and the structure so formed. The invention further provides a spacer formed around the capacitor to electrically isolate portions of the capacitor
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.