Methods and apparatus for testing semiconductor and integrated circuit structures
US6504393B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 1997 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Jul 15, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/307
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of testing a semiconductor structure such as a finished or part-finished semiconductor wafer, a die on such a wafer, part of such a die, or even one functional element (e.g. a transistor or memory cell) of such a die. The method includes the steps of charging at least a part of the semiconductor structure; applying an electric field perpendicular to a surface of the structure while charging so as to determine charging potential and polarity (i.e. charging either positively or negatively); interrogating the structure including the charged part with a charged particle beam, such as an electron beam, so as to obtain voltage contrast data for the structure; and analyzing the data to determine the functionality of the element. Apparatus according to the invention for testing semiconductor structures, includes: a system for applying charge to at least part of the semiconductor structure, such as an electron beam, flood gun or mechanical probe; an electric field generator, typically an electrode spaced from the surface of the structure, which applies an electric field perpendicular to a surface of the structure so as to determine the potential and polarity of the charge applied t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.