Configuration for trimming reference voltages in semiconductor chips, in particular semiconductor memories
US6504394B2 · kind B2 · utility
10Cited by
4References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 14, 2000 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Dec 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A circuit configuration for trimming reference voltages in semiconductor chips. The circuit configuration contains a test logic unit and a trimming circuit for trimming at the chip level the reference voltages. The reference voltages are compared to an externally supplied comparison voltage and the reference voltage is varied by the trimming circuit if it does not match the comparison voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.