Double boosting scheme for NAND to improve program inhibit characteristics
US6504757B1 · kind B1 · utility
64Cited by
2References
7Claims
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Key dates
| Filing date | Aug 3, 2001 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Aug 3, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for boosting potential in the channel of unselected memory cells on a selected bit-line. In this method, a first voltage is applied to all the word-lines of the memory cells in the string. A second voltage is then applied to word-lines adjacent the selected word lines to isolate the selected memory cell. Next, a programming voltage is applied to the selected word-line. In one embodiment, a time delay is applied between applying the second voltage and applying the third voltages to ensure isolation of the selected memory cell before applying the third voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.