Redundancy selection in memory devices with concurrent read and write
US6504768B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2000 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Nov 23, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices having redundancy selection circuitry are suited for high-performance memory devices, with particular reference to synchronous non-volatile memory devices capable of concurrent read and write operations. Such memory devices include a redundancy comparator for comparing address signals applied to the memory device to known defective address, and for selecting redundant elements if a match is identified. A redundancy comparator includes at least one redundancy compare latch circuit, each redundancy compare latch circuit having a mapping latch circuit, a read address compare circuit coupled to the mapping latch circuit, and a write address compare circuit coupled to the mapping latch circuit. The read address compare circuit and the write address compare circuit thus share the same mapping latch circuit. Such circuits are capable of simultaneously comparing a read address signal and a write address signal, thus facilitating concurrent read and write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.