Semiconductor memory device employing row repair scheme
US6504769B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2001 |
| Grant date | Jan 7, 2003 |
| Priority date | — |
| Expiry date | Mar 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having a plurality of cell blocks includes: a fuse box group, coupled to the cell blocks, for generating a repair signal in response to a row address signal; a repair signal summation unit for generating a repair summation signal for controlling a repair operation in response to the repair signal; a block selection signal generation unit for generating a block selection signal for selecting a cell block to be repaired in response to the repair summation signal and a block selection address signal; and a repair row decoding unit for driving a redundant word line in response to the repair signal and a block selection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.